Synchronous semiconductor integrated circuits are generally realized in such a manner that a flip-flop circuit in a circuit is synchronized to a clock. In the synchronous semiconductor integrated circuits, the maximum value of a delay in propagation time between flip-flop circuits in a circuit determines the frequency of the clock to which the flip-flop circuits are synchronized. It is not true that a shorter delay in propagation between flip-flop circuits is always preferable. That is, because of a period of time after which the flip-flop circuit will be able to read data, or a time difference of a clock supplied to two flip-flop circuits connected by a propagating signal, a delay in propagation of a certain time (a period of time equal to or longer than a certain time) is required to be defined between individual flip-flop circuits. For example, without such a delay of a certain time between flip-flop circuits connected by a propagating signal, a previous clock signal is picked up by the flip-flop circuit as data. This results in a failure. Such a failure is referred to as a hold error. Techniques for preventing the hold error have been proposed (PTLs 1-8, and NPL 1).
A system for designing a semiconductor integrated circuit in NPL 1 comprises semiconductor integrated circuit data, a circuit delay measurement system, a delay buffer insertion deciding system, and a delay buffer inserting system. In this system, the circuit delay measurement system first measures a delay in a pair of flip-flop circuits between which a signal propagates. Next, the delay buffer insertion deciding system decides where a hold error is likely to occur using a result of the measurement. The delay buffer inserting system then inserts a delay buffer for generating a delay to prevent occurrence of a hold error. For example, in a case that two flip-flop circuits are directly connected with each other without any circuit element for generating a delay and a hold error is expected to occur, a delay gate is inserted by this system for designing a semiconductor integrated circuit. This eliminates a hold error (see FIG. 9).
A system for designing a semiconductor integrated circuit as disclosed in PTL 1 comprises semiconductor integrated circuit data, a circuit delay measurement system, a latch circuit insertion deciding system, and a latch circuit inserting system. In this system, the circuit delay measurement system first measures a delay in a pair of flip-flop circuits between which a signal propagates. Next, the latch circuit insertion deciding system decides where a hold error is likely to occur using a result of the measurement. Then, the latch circuit inserting system inserts a latch circuit that blocks signal transmission in a half of a clock cycle and permits signal transmission in the other half of a clock cycle. As a result, a delay equivalent to a half of a clock cycle is given to a signal line with a hold error. For example, in a case that two flip-flop circuits are directly connected with each other without any circuit element for generating a delay and a hold error is expected to occur, a latch circuit is inserted by this semiconductor integrated circuit design system. Thus, a delay equivalent to a half of a clock cycle is inserted. This eliminates a hold error (see FIGS. 9, 10).
In PTL 2, a design technique using a latch circuit is proposed. However, the technique is extremely difficult to adapt to a design technique applied to common flip-flop-based synchronization circuits.
According to PTL 3, there is a description as “If a flip-flop circuit under any of these conditions can be divided into latch circuits, the division is determined according to conditions such as a delay time in a preceding path and a delay in a subsequent path.” There is also a description as “the clock cycle period is set longer by a predetermined value and the logic circuits are arranged, and the flip-flop circuits related to an error path on which an error for the target clock cycle occurs are replaced by latch circuits to rearrange the logic circuits in the pipeline design using flip-flop circuits. It is, therefore, possible to increase the permissible maximum logic delay time of a logic path and to easily design a pipeline.”
According to PTL 4, there is a description as “a signal line connecting system in accordance with this embodiment is comprised of: a logic design data memory section for storing therein logic design data for a semiconductor device; a program storage section for storing therein programs or the like for analyzing timing of signal lines to create a new via connection pattern; a position/connection information memory section for storing therein information about the position and connection of logic elements; a timing information memory section for storing therein timing analysis information for a signal delay in propagation time in a signal line; a via information memory section for storing therein via information for a signal line formed in a different redistribution layer and connected through a via; a processing control section comprising means for executing a series of signal line connecting processing; an output device for outputting a result of the processing via an input/output control section; and an input device for inputting a command and the like to the processing control section.” There is also a description as “There are provided signal line connecting method and system in which a signal delay in propagation time sufficient for controlling timing between logic elements is given.”
According to PTL 5, there is a description as “for hierarchical design, comprising: a plurality of timing distribution production sections individually provided corresponding to a plurality of design hierarchical layers, and each of which receives block information regarding a function of a circuit from a respective timing information database having netlist information regarding a wiring line scheme and outputs a respective timing distribution value obtained by distributing a delay value produced by a delay element of the circuit; and an inter-hierarchical layer association manager for dynamically changing connections between said plurality of timing distribution production sections and transmitting and receiving modification information regarding the respective timing distribution value to and from said plurality of timing distribution production sections.” There is also a description as “when the timing specifications are changed, a range of the influence of the change can be referred to immediately, and consequently, a reference mistake upon such change of the specifications is eliminated. Further, the combination of provisional wiring and actual wiring can achieve both of augmentation of an execution speed of floor planning and augmentation of an accuracy. Furthermore, a hierarchical entity can be used and a distributed design environment can be constructed. Further, in top-down design, only a necessary portion can be particularized, and it can be examined whether timing specifications divided by trial and examination are appropriate or not by one design team. Consequently, problems upon implementing can be estimated and otherwise possible iterations can be reduced.”
According to PTL 6, there is a description as “In the delay optimization unit, there is the step of inserting a level latch circuit in a signal path violating said minimum delay constraints, wherein the step of inserting comprises the steps of: calculating the frequency of overlap of each output terminal included in said synchronous sequential circuit with signal paths violating the minimum delay constraints; and inserting said level latch circuit in a signal path in the descending order of said frequency of overlap such that an LSI layout pattern area of said synchronous sequential circuit is minimized.” There is also a description as “the calculation processing time can be reduced because the maximum delay time is not affected. Moreover, the increase in the LSI layout pattern area in the synchronous sequential circuit can be reduced.”
According to PTL 7, there are a description as “a method for designing a semiconductor integrated circuit using pattern data for a flip flop function device including a flip flop forming means for receiving a clock signal and a data signal, a latch forming means for receiving the clock signal and an output signal of the flip flop forming means, a first output terminal for outputting a signal from the flip flop forming means, and a second output terminal for outputting a signal from the latch forming means, the method characterized in including the steps of designing a circuit by forming a data path with the first output terminal; inspecting hold time in a latter stage device of the data path; and connecting the latter stage device to the second output terminal instead of the first output terminal when found in the inspection that there is a possibility of occurrence of a hold time violation,” and a description as “an apparatus for designing a semiconductor integrated circuit using pattern data for a flip flop function device including a flip flop forming means for receiving a clock signal and a data signal, a latch forming means for receiving the clock signal and an output signal of the flip flop forming means, a first output terminal for outputting a signal from the flip flop forming means, a second output terminal for outputting a signal from the latch forming means, the apparatus characterized in including: a design processing means for designing a circuit by forming a data path with the first output terminal; a hold time inspecting means for inspecting hold time in a latter stage device of the data path; and a data path correcting means for connecting the latter stage device to the second output terminal instead of the first output terminal when found in the inspection that there is a possibility of occurrence of a hold time violation.”
According to PTL 8, an object is “to provide a method of designing layout of a semiconductor integrated circuit in which, in a case that there is no space in a hold error path for disposing a buffer for eliminating a hold error or in a case that there is space for disposing the buffer but a setup error is introduced, a point for inserting a buffer preventing a new delay error can be searched for by moving other cells, duplicating a line or modifying line connection, thereby avoiding repetition of ECO layout”, and there is a description as “a method of designing layout of a semiconductor integrated circuit, the method characterized in comprising the steps of performing initial positioning/connection by initial positioning/connecting means based on a netlist for a semiconductor integrated circuit to create layout information; performing extraction of line resistance and line capacity, delay calculation, and static timing analysis by RC extraction/delay calculation/static timing analysis means based on said layout information to create line resistance/line capacity information and hold error path/slack information; making a decision about the presence/absence of a hold error by hold error presence/absence deciding means based on said hold error path/slack information, and in a case that a hold error is present, creating information on a penalty required to search for a point for inserting a buffer for eliminating a hold error by penalty information creating means based on said layout information and said hold error path/slack information; and performing search for and determination of said insertion point and delay coordination by buffer insertion point searching/determining/delay coordinating means based on said penalty information.” However, no description of a flip-flop circuit is found in PTL 8.
[Citation List]
[Patent Literature]
PTL 1: JP-P2677256B
PTL 2: JP-P2005-277909A
PTL 3: JP-P2003-234643A
PTL 4: JP-P2005-26390A
PTL 5: JP-P2007-188517A
PTL 6: JP-P1997-008143A
PTL 7: JP-P2007-142094A
PTL 8: JP-P2008-217642A
[Non Patent Literature]
NPL 1: “Circuits, Interconnections, and Packaging for VLSI,” edited and translated by Kisaburou NAKAZAWA and Hiroshi NAKAMURA, published by MARUZEN Co., Ltd., pp. 356-358